This invention relates to programmable logic devices (xe2x80x9cPLDsxe2x80x9d), and more particularly to input/output (I/O) circuitry that may be used to couple the PLDs to external circuitry having multiple signal interfaces.
Programmable logic devices are integrated circuits that are used to implement combinational and/or sequential digital functions that may be defined by a designer and programmed into the PLD. In this manner, PLDs may be configured by a user to implement, for example, any Boolean expression or registered function with built-in logic structures. Once configured, the user must connect the PLD to external circuitry that provides input signals to, and receives output signals from, the PLD. Often, integrated circuits are used to interface with several bus structures and/or control signals, each of which may utilize different signaling levels for communication.
One deficiency of conventional PLDs and their I/O circuitry is that each PLD must be configured to operate with specific external circuitry. For example, if a user utilizes Transistor-to-Transistor Logic (TTL) or Complementary Metal-Oxide Semiconductor (CMOS) external circuitry, the PLD must be configured to provide the appropriate drive signals. This often requires the use of translation circuitry. For example, Wong et al. U.S. Pat. No. 5,600,267 describes a CMOS circuit for translating a signal from Current-Mode-Logic (CML) to CMOS logic voltage levels. This deficiency is even more apparent in view of the programmable nature of PLDs and the flexibility provided to the end users. Another example of this requirement is described in Nhu U.S. Pat. No. 4,975,602, in which a multi-logic interface box is described that has a multi-connector coupler that provides different logic level conversions.
Further, the nature of PLDs, as semiconductor devices, is that they are susceptible to a wide range of potential hazards, such as electrostatic discharge (ESD). To avoid these potential problems, care must be taken in connecting the PLD pins to external circuitry. Any pins which are used as input pins should preferably be driven by an active source (including bi-directional pins during input operations). Additionally, unused pins are typically tied to ground to avoid the potential of additional DC current and noise being introduced into the circuits.
Output loading of the PLD I/O pins is typically resistive and/or capacitive. Resistive loading exists where the device output sinks or sources a current during steady-state operation (e.g., TTL inputs, terminated buses, and discrete bipolar transistors). Capacitive loading typically occurs from packaging and printed circuit board traces. Further, an important design consideration of the interface between the PLD and external circuitry is that the target device can supply both the current and speed necessary for the given loads.
One deficiency of Wong, Nhu and other known interface translators is the limited scope with which the circuitry may be used. Often these devices are designed such that either the interface only supports a single signaling type, or that external circuitry, such as Nhu""s interface box, is required to act as a transceiver. More importantly, these devices often provide only a single interface on all of the input/output pins of the device at a single time.
In view of the foregoing, it would be desirable to be able to provide an I/O architecture that provides the capability to drive multiple logic standards.
It also would be desirable to be able to provide an I/O architecture having the capability to selectively drive different I/O cells on a single integrated circuit with different logic standards.
It further would be desirable to be able to provide an I/O architecture that may be programmed by a user to select any one of several logic standards for individual I/O cells of ah integrated circuit, such that a single PLD may be used with external circuitry that operates at different logic levels.
These and other objects are accomplished in accordance with the principles of the present invention by providing an I/O architecture that includes programmable I/O cells having multiple drivers, each of which provides an interface to a different signaling level. In a preferred embodiment of the present invention, PLDs are provided having programmable I/O cells that interface with, for example, High-Speed Transistor Logic (HSTL) (both terminated and non-terminated), Stub-Series Terminated Logic for 3.3 volts (SSTLxe2x80x943), Gate Transistor Logic (GTL), TTL, CMOS, open drain and logic standards. Those skilled in the art will understand that other logic standards, both those presently available and others still to be developed, may be incorporated into the I/O cells such as those described herein without departing from the scope of the present invention.
The preferred embodiment of the present invention provides programmable I/O cells that each may be individually accessed at the same time the PLD programming file is downloaded into the PLD. Each I/O cell includes multiple drivers, only one of which is selected by the programming file. The other drivers are then disabled by in any conventional manner (such as tristating). The number of interfaces supported is only limited by the number of buffers placed in the silicon. A further advantage of the I/O cells of the present invention is that they may be configured such that a single programming bit may be used to set each cell, and all of the cells may be programmed at once via an ENABLE signal.